1. Field of the Invention
The present invention relates to the field of baseband computer networks. Specifically, the present invention relates to a method and apparatus utilized by a dual speed 10/100 Mb/s physical layer device. The dual speed device provides support for transmitting waveshape information compatible with the Institute of Electrical and Electronic Engineers (IEEE) 802.3 Clause 14, 10 million bits per second (10 Mb/s) Physical Layer specification, i.e., IEEE 802.3 Standard 10BASE-T Ethernet, over a service interface in the physical layer. The interface, although not specified in IEEE 802.3, is commonly used in the single speed implementation of 100 million bits per second (100 Mb/s) Local Area Network (LAN) physical layer devices compatible with the Physical Layer specifications defined in the IEEE 802.3u Supplement (excepting Clause 23 and 26), i.e., the IEEE 802.3 Standard 100BASE-TX Ethernet.
2. Description of the Related Art
Overview of 100 Mb/s Baseband Networks
To better appreciate and understand the present invention, a brief overview of relevant aspects of 100 Mb/s baseband local area networks follows. The operation of a Local Area Network (LAN) is often described in terms of the International Standards Organization (ISO) seven-layer Open Systems Interconnection (OSI) abstract reference model. Referring to FIG. 1, the relationship between the seven-layer OSI reference model 100 and the IEEE 802.3 architectural layers for 1 Mb/s to 20 Mb/s operation model 110 and 100 Mb/s operation model 115 are shown.
100BASE-T is an IEEE standard 802.3 Physical Layer specification for 100 Mb/s Ethernet LANs. The standard extends the speed of the 802.3 Media Access Controller (MAC) to 100 Mb/s while utilizing the existing MAC service interface 102 of MAC 200. MAC service interface 102 is connected through a Reconciliation layer 103 and a Media Independent Interface layer 130 to a 100 Mb/s physical layer device sublayer 104. The physical layer may be implemented according to one of two additional physical layer specifications, 100BASE-T4 and 100BASE-X. 100BASE-T4 specifies the use of four pairs of category 3, 4 or 5 Unshielded Twisted Pair (UTP) wire. 100BASE-X supports two embodiments: 100BASE-TX and 100BASE-FX. 100BASE-TX specifies the use of 2 pairs of category 5 UTP or shielded twisted pair (STP) wire. 100BASE-FX specifies the use of 2 optical fibers. Generally, the term 100BASE-X is used when referring to characteristics common to both 100BASE-TX and 100BASE-FX.
100BASE-X is an IEEE standard 802.3 Physical Layer specification for 100 Mb/s LANs that uses the FDDI signaling standards. 100BASE-X encompasses 100BASE-TX (which references ANSI X3T9.5 TP-PMD/312, Revision 2.2, FDDI Twisted Pair Physical Medium Dependent (PMD) sublayer), and 100BASE-FX (which references ISO 9314-3, 1990, Fiber Distributed Data Interface (FDDI)--Part 3: Token Ring PMD sublayer).
As described in clause 28 of IEEE standard 802.3u, Auto-Negotiation is an optional function that allows a network device, such as a workstation, switch or repeater, coupled to a point-to-point link segment, to advertise the modes of operation of which it is capable to a network device at the other end of the point-to-point link segment and detect corresponding operational modes that the other network device may be advertising. Auto-Negotiation provides the capability for future technology upgrades and can be modified to advertise such modes of operation as types of physical layer devices available, full-duplex communication, and flow control. Auto-Negotiation further provides, through the use of the Parallel Detect Algorithm, the ability to detect and interoperate with legacy, non-Auto-Negotiation, half duplex, 10BASE-T, 100BASE-TX and 100BASE-T4 based nodes where applicable. Auto-Negotiation is designed for LANs implemented using unshielded twisted pair (UTP) copper wire and the well known, ISO/IEC 8802, eight-pin modular jack (RJ-45 connector). The signaling mechanism used in Auto-Negotiation is backwards compatible with the installed base of 10BASE-T baseband computer networks as defined in IEEE 802.3 Clause 14.
The 10BASE-T standard employs a discontinuous signaling method over the transmission medium. When data is not being sent over the copper wire, the voltage on the wire is zero, with the exception of an occasional Link Test Pulse. The Link Test Pulse, as defined in IEEE standard 802.3, Clause 14, signals that an active link connection exists. The Link Test Pulse is generally a 100 nanosecond positive pulse that repeats approximately every 16 milliseconds. Auto-Negotiation refers to the 10BASE-T Link Test Pulse as the Normal Link Pulse (NLP). Auto-Negotiation uses multiple Link Test Pulses to form a burst referred to as a Fat Link Pulse (FLP) Burst, as a signaling mechanism. Auto-Negotiation substitutes the FLP Burst in place of the single 10BASE-T Link Test Pulse. The FLP Burst encodes the data (identifying modes of operation) transmitted by the Auto-Negotiation function.
100BASE-T Architecture and Nomenclature
With reference to FIG. 1, the 100BASE-T standard extends the IEEE standard 802.3 Media Access Control (MAC) sublayer 200 to 100 Mb/s by coupling the MAC sublayer to a 100 Mb/s physical layer. The physical layer is comprised of additional sublayers including the Physical Coding Sublayer (PCS) 140, Physical Medium Attachment (PMA) sublayer 150, Physical Medium Dependent (PMD) sublayer 160 and, in a 100BASE-TX environment, an optional Auto-Negotiation (AutoNeg) sublayer 170. The PMD sublayer 160 encompasses the Medium Dependent Interface (MDI) 180. The MDI provides the medium attachment, including the connector, to the medium 190, such as UTP or STP wiring.
Reconciliation Sublayer
The Reconciliation Sublayer maintains the same interface to the MAC layer for 100 Mb/s operation as for 1 Mb/s to 20 Mb/s operation by reconciling the differences between the PLS, AUI, and MAU architectures described in IEEE 802.3 clauses 5 through 20 and the MII based architecture described in 802.3u.
Media Independent Interface (MII)
The MII sublayer provides, among other things, an interconnection between the MAC sublayer and Physical layer devices. As the name implies, this layer was designed to clearly separate the MAC sublayer from medium dependent issues. The MII is designed to support multiple physical layer devices operating at different speeds, e.g., 10 Mb/s or 100 Mb/s. The MII defines receive and transmit directions for data transfer, each comprised of a clock, error, enable and four data signals, for a total of fourteen signals. The MII can be embodied, for example, in an integrated circuit to integrated circuit interface with traces on a single printed circuit board (PCB), a motherboard to daughterboard interface across at least two PCBs, or a cable with appropriate connectors coupling two PCBs.
PCS Sublayer
With reference to FIG. 3, the PCS sublayer 330 provides a Media Independent Interface (MII) 320 to a Reconciliation sublayer 310 which, in turn, provides an interface between the MAC sublayer 300 and the Physical sublayers. The PCS sublayer transfers information with the MAC sublayer via asynchronous, nibble-wide (i.e., 4-bit wide) transmit and receive lines 321 and 322, respectively. The nibbles passed to the MAC sublayer are derived from code groups of 5 bits each (discussed below), which, in turn, are received from the medium via the PMA 340, PMD 350 and MDI 360. In a 100BASE-X environment, a PCS receive code bits process 339 accepts a continuous stream of 5-bit code groups at a rate of 25 million code groups per second (125 million bits per second). Each 5 bits that make up a code group is converted to a 4-bit value by a 4B5B decoder before being passed to the MAC sublayer 300 at a data rate of 25 million nibbles per second (100 million bits per second).
Likewise, a PCS transmit code bits process 338 transmits a continuous stream of code group bits generated by a 4B5B encoder based on bits received from the MAC sublayer via nibble-wide data line 321. Line 321 transmits data received from the MAC sublayer at a rate of 25 million nibbles per second, while transmit code bits process 338 transmits code group bits at a rate of 25 million code groups per second (125 million bits per second).
Code Groups
PCS 330 converts 4 bits received from RS 310 into 5-bit code groups via a 4B5B encoder. Likewise, a 4B5B decoder converts 5-bit code groups received from {MA} 340 into 4-bit nibbles. The IEEE Standard 802.3u defines a code group as a consecutive sequence of five code bits that are interpreted and mapped by the PCS. Code groups are defined in ISO 9314-1 (Fibre Distributed Data Interface (FDDI)--PHY, Table 1. Therein, a 4B5B data coding format is described in which a 4-bit nibble is mapped into a five bit code group. The nibbles of data, which represent hexadecimal digital words, are aligned to a 25 MHz clock. The resulting data rate of 100 Mb/s is converted by 4B5B encoding into a code bit rate of 125 Mb/s. Implementors may choose a 100 Mb/s/125 Mb/s serial implementation of the 4B5B encoding process, or a 4-bit wide to 5-bit wide parallel implementation of the 4B5B encoding process clocked at 25 MHz.
PCS Mapping of Data between MII and PMA
When receiving data from the PMA sublayer, the PCS 330 maps a nonaligned code-bit data line 334 from the PMA 340 to an aligned, 4-bit wide data line 322 across the MII 320. On transmitting data to the PMA, the PCS 330 maps an aligned, nibble-wide data line 321 across the MII to a nonaligned code-bit data line 333 to the PMA. Data bits are buffered on both transmission from and reception at the PCS by the transmit code bits process 338 and receive code bits process 339, respectively.
Upon receipt of a nibble from the MII 320, a 4B5B encoder in transmit process 324 of PCS 330 encodes the nibble into a 5-bit code group, according to the ISO 9314-1 FDDI PHY standard. Each 5-bit code group is buffered and transmitted to the PMA 340 as a serial string of five data bits by transmit code bits process 338. Likewise, upon receipt of a serial string of code group bits from PMA 340 over line 334, the receive code bits process 339 of PCS 330 buffers and deserializes 5-bit code groups before passing the code groups to a 4B5B decoder in receive process 325. The 4B5B decoder converts the code groups into nibbles and passes the nibbles on to MII 320, again according to the ISO 9314-1 FDDI PHY standard.
Carrier Detection and Data Transmission
PCS 330 sends 5-bit code groups to the PMA as described above. When not transmitting data packets, the PCS transmit code bits process 338 continually sources idle (I) code groups to the PMA. When the MII indicates to the PCS that data is ready to be transmitted, the transmit process 324 transmits a start of stream delimiter (SSD) (i.e., a J, K code group pair according to the above referenced FDDI PHY standard) to the PMA 340. Data received at the PCS sublayer from the MII 320 is then encoded into 5-bit code groups and transmitted to the PMA 340.
The receive code bits process 339 in the PCS sublayer receives code bits from the PMA 340. The receive bits are serially loaded into a 10-bit wide sliding window at a rate of 125 Mb/s. Most recently received code bits enter the sliding window at a location receive bit (RX BIT) 0 within the window. As each new bit is received, the existing bits in the window are shifted one position. When a code group of 5 bits is detected in the window, it is forwarded over line 332 to a 4B5B decoder in receive process 325, where the code group is converted to a nibble and passed to MII 320.
IEEE Architectural Model versus Implementation
IEEE 802.3 Physical Layer specifications provide an architectural model upon which to implement an interface device that couples a MAC layer interface to a physical medium operating at 1 Mb/s through 20 Mb/s or 100 Mb/s.
As discussed above, the architectural model focuses on a logical and functional division of services provided by each layer in the model and communication between the various layers comprising the functions. However, the actual implementation of a device (i.e., the electrical and mechanical components and their interconnection between the medium and MAC) in accordance with the IEEE 802.3 standard may substantially depart from the logical and functional divisions defined by the architectural model. It is understood by those of skill in the art that so long as the actual implementation adheres to the exact specification of the physical medium signals set forth in the Medium Dependent Interface (MDI) specification for 100 MB/s or the Medium Attachment Unit (MAU) specifications for 10BASE-T, the implementation need not exactly follow the logical and functional divisions defined in the architectural model. What is desired is an implementation of a physical layer interface device that provides efficient and economical configuration of integrated circuits and the like based on considerations of technology rather than considerations of logical functions so long as the implementation adheres to the exact specification of the physical medium signals and medium access operations set forth in the applicable medium to MAC/LLC specifications.
All commercial implementations of physical layer devices adhering to the IEEE 802.3u, 100BASE-TX standard utilize both analog circuit functions and digital circuit functions. These functions may be combined in a single device or split among multiple devices. If analog and digital functions are combined in a single device, mixed signal design methodologies are required in the engineering process. The establishment of engineering competency of mixed signal techniques is significantly more complex, expensive and risky than that for design of Application Specific Integrated Circuits (ASICs) utilizing digital cells in an "off the shelf" core. In the generic digital ASIC approach, standard cells, already placed in silicon, are connected together using custom metal layers to form the custom integrated circuit. Utilizing this established design methodology requires that the functionality of the ASIC be limited to only digital functions.
If the digital ASIC approach is to be used, the various analog functions such as clock recovery, waveshaping, and high speed digital operations (e.g., at 125 MHz) that are not compatible with low cost ASICs must be performed by one or more devices in the analog front end. This split between basic, low cost digital ASIC functionality and the other required physical layer device functions represents a service layer interface that splits the physical layer, which is based on commercial implementation and does not match any of the standardized architectural service layer interfaces. What is needed is a dual speed 10/100 Mb/s physical layer device service interface based on this commercial implementation.
Technological advances in analog circuitry presently do not keep pace with the significant technological advances in Complementary Metal Oxide Semiconductor (CMOS) Integrated Circuit (IC) technology. Advances in digital circuitry continue to produce smaller gates and die sizes, increase functionality and reduce costs. What is needed then, is a physical layer device whose implementation separates the digital integrated circuitry from the analog circuitry to take advantage of the improvements in digital ICs without affecting stable, analog circuitry.
It is further desirable for the analog front end of a 100BASE-TX only repeater to be able to support Auto-Negotiation Fast Link Pulse signaling without the requirement of supporting all the additional design issues of 10BASE-T functionality such as waveshape acceptance/rejection and a different clock speed. A desirable benefit of splitting the generation, receipt and clocking of the waveform on the medium from the process of data coding is the possibility of future line codes, without a change in analog physical layer device silicon, for applications such as Asynchronous Transfer Mode (ATM) to the desktop, or direct access to the Global Synchronous Digital Hierarchy (SDH) or LANs with error correction. An alternate data coding that used the 10BASE-T or 10BASE-X waveshapes would pass through the analog physical layer device for processing by a specialized digital ASIC.
Further, what is needed is an implementation of a physical layer device conforming to the IEEE 100BASE-TX standard that also provides 10BASE-T signaling to provide support for dual speed media access controller devices, e.g., a 10/100 Mb/s MAC device.